SoC Design Verification Engineer

Key Responsibilities– 1. Subsystem and SoC Functional Verification 2. System Verilog/UVM Testbench Reuse and Enhancement 3. Processor–Based C Test Development and Verification 4. Regression Execution, Debugging, and Coverage Closure 5. Verification Planning and Collaboration Required Technical Skills Essential Skills Strong hands–on experience in digital design verification using System Verilog and UVM. Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components. Good understanding of constrained–random verification, functional coverage, assertions, scoreboards, and checkers. Experience in subsystem–level or SoC–level functional verification. Strong understanding of SoC architectures, bus protocols, register interfaces, and processor–controlled peripherals. Experience developing, executing, or debugging embedded C tests for processor–based SoC verification. Ability to debug complex RTL simulation failures using industry–standard simulators and waveform debugging tools. Experience executing regressions, analyzing failures, and driving functional coverage closure. Working knowledge of scripting languages such as Python, Perl, or shell scripting. Familiarity with version control systems and verification development workflows